The present disclosure relates to circuit design and, more particularly, to techniques for selective boundary overlay insertion for hierarchical circuit design.
Hierarchical circuit design refers to techniques in which layers of abstraction are used to enable concurrent design of embedded components and top-level components and to enable reduced memory requirements by hiding self-contained portions of a design from automation or verification tools. The desire to abstract embedded components can result in false verification failures that do not show up when the hierarchy is flattened but may prevent a piece of the hierarchy from achieving clean checking grades. Moreover, this can drown out real failures, potentially causing design defects.